In this paper, a two-dimensional (2D) Crank-Nicholason (CN) finite difference time domain (FDTD) method is proposed for VLSI interconnect/substrate characterization. Through rigorous truncation and dispersion error analyses, a guideline on using this technique is presented. Several iterative solvers are investigated to accelerate the solution of the CN-FDTD scheme. Numerical examples are given to demonstrate the accuracy and the efficiency of the proposed algorithm.
R. Qiang et al., "A CN-FDTD Scheme and Its Application to VLSI Interconnects/Substrate Modeling," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2004, Santa Clara, CA), vol. 1, pp. 97-101, Institute of Electrical and Electronics Engineers (IEEE), Aug 2004.
The definitive version is available at https://doi.org/10.1109/ISEMC.2004.1350004
IEEE International Symposium on Electromagnetic Compatibility (2004: Aug. 9-13, Santa Clara, CA)
Electrical and Computer Engineering
Keywords and Phrases
2D FDTD Method; CN-FDTD Scheme; Crank-Nicholason Method; VLSI; VLSI Interconnect/Substrate Characterization; Dispersion Error Analysis; Finite Difference Time Domain Method; Finite Difference Time-Domain Analysis; Integrated Circuit Interconnections; Integrated Circuit Modelling; Iterative Methods; Iterative Solvers; Truncation Error Analysis; Two-Dimensional FDTD Method; Very Large Scale Integration; Finite Difference Methods; Time Domain Analysis; Finite Wordlength Effects; Error Analysis; Magnetic Analysis; Iterative Algorithms; Equations
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Article - Conference proceedings
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Aug 2004