Performance and reliability are two of the most crucial issues in today's high-performance instrumentation and measurement systems. High speed and compact density multistage interconnection networks (MINs) are widely-used subsystems in different applications. New performance models are proposed to evaluate a novel fault tolerant MIN arrangement, thereby assuring performance and reliability with high confidence level. A concurrent fault detection and recovery scheme for MINs is considered by rerouting over redundant interconnection links under stringent real-time constraints for digital instrumentation as sensor networks. A switch architecture for concurrent testing and diagnosis is proposed. New performance models are developed and used to evaluate the compound effect of fault tolerant operation (inclusive of testing, diagnosis, and recovery) on the overall throughput and delay. Results are shown for single transient and permanent stuck-at faults on links and storage units in the switching elements. It is shown that performance degradation due to fault tolerance is graceful while performance degradation without fault recovery is unacceptable.


Electrical and Computer Engineering

Keywords and Phrases

MIN Performance; MIN Reliability; Compact Density MIN; Concurrent Fault Detection; Concurrent Testing/Diagnosis; Delays; Digital Instrumentation; Digital Instrumentation Systems; Fault Diagnosis; Fault Recovery; Fault Tolerance; Fault Tolerant Multistage Interconnection Networks; Interconnection Rerouting; Measurement Systems; Multistage Interconnection Network (MIN); Packet Switching; Performance Degradation; Permanent Stuck-At Faults; Redundancy; Redundant Interconnection Links; Sensor Networks; Storage Units; Telecommunication Equipment Testing; Telecommunication Network Reliability; Throughput; Transient Faults; Diagnosis; Instrumentation; Performance Analysis

International Standard Serial Number (ISSN)

0018-9456; 1557-9662

Document Type

Article - Journal

Document Version

Final Version

File Type





© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Oct 2003