Doctoral Dissertations

Keywords and Phrases

Corona Discharge; Electrostatic Discharge; On-chip ESD; SEED; Through-silicon Via

Abstract

Systematic ESD analysis provides good pre-compliance to ESD robustness evaluation on the electronic device from device level to component/system level to on-chip level. The whole process involves corona discharge on display, system level ESD analysis on PCB for race condition and transient response and 3D IC package impact to on-die ESD.

ESD to the display cover glass can damage touchscreen traces by sparkless corona discharges on the glass surface. A non-linear time dependent transmission-line model is proposed to model corona streamer propagation in terms of the coupling current and propagation speed. Results are highly promising to model the corona discharge without measurement and parameter tuning in the future.

System level ESD characterization involves the black-box characterization of on-chip ESD protection devices and System efficient ESD design (SEED) considering the race condition between on-chip ESD and off-chip TVS. System-level ESD with USB repeater using the on-chip model and the off-chip TVS and system components for race condition and transient response are modeled.

ESD transient behavior on through-silicon via and 3D IC package impact to on-die ESD protection characteristics are further investigated for on-chip level evaluation. ESD to TSV transient characteristics under different voltage levels and rise time were analyzed. By modeling multi-die stack of TSV and assessing package-level influences, the study evaluates on-die ESD protection in context of 3D IC packaging effects. Potential solutions for package design and on-die ESD protection are discussed, addressing ESD behavior characterization challenges introduced by package impacts.

Advisor(s)

Kim, DongHyun (Bill)

Committee Member(s)

Song, Chiuk
Hwang, Chulsoon
Beetner, Daryl G.
Khilkevich, Victor

Department(s)

Electrical and Computer Engineering

Degree Name

Ph. D. in Electrical Engineering

Publisher

Missouri University of Science and Technology

Publication Date

Summer 2025

Journal article titles appearing in thesis/dissertation

Paper I, found on pages 4–25, has been published in 2024 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+ SIPI), and is intended to be extended and submit to IEEE Transactions on Electromagnetic Compatibility.
Paper II, found on pages 26–54, has been published in IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 6, pp. 1802-1811, Dec. 2022.
Paper III, found on pages 55–80, has been submitted to IEEE Transactions on Components, Packaging and Manufacturing Technology.

Pagination

xiii, 83 pages

Rights

© 2025 Zhekun Peng , All Rights Reserved

Document Type

Dissertation - Open Access

File Type

text

Language

English

Thesis Number

T 12516

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