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| Title: | Asynchronous nanowire crossbar architecture for manufacturability, modularity and robustness | |
| Alternate Title: | Clock-free nanowire crossbar architecture based on Null Conventional Logic (NCL) Defect-tolerant gate macro mapping and placement in clock-free nanowire crossbar architecture. Evaluation of defect-tolerant mapping and placement techniques for asynchronous crossbar architecture. | |
| Author (s): | Bonam, Ravi Kiran, 1985- | |
| Advisor(s): | Choi, Minsu | |
| Keywords: | Null Conventional Logic (NCL) | |
| Issue Date: | 2008 | |
| Publisher: | Missouri University of Science and Technology | |
| Citation: | Bonam, Ravi. "Asynchronous Nanowire Crossbar Architecture for Manufacturability, Modularity and Robustness" Master's Thesis, Computer Engineering, Missouri University of Science and Technology, 2008. | |
| Abstract: | "This thesis spotlights the dawn of a promising new nanowire crossbar architecture, the Asynchronous crossbar architecture, in the form of three different articles. It combines the reduced size of the nanowire crossbar architecture with the clock-free nature of Null Conventional Logic, which are the primary advantages. The first paper explains the proposed architecture with illustrations, including the design of an optimized full adder. This architecture has an elementary structure termed as a Programmable Gate Macro Block (PGMB) which is analogous to a threshold gate in NCL. The other two papers concentrate on mapping and placement techniques which are important due to defects involved in crossbars. These defects have to be tolerated and logic has to be routed appropriately for successful functioning of the circuit"--Introduction, p. [1]. | |
| Type: | Thesis/Dissertation text | |
| Copyright Notice: | These materials are protected under copyright by the original author. | |
| Link to this page: | ||
| URL: | ||
| Full Text: |
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| title | Asynchronous nanowire crossbar architecture for manufacturability, modularity and robustness | |
| title.alternative | Clock-free nanowire crossbar architecture based on Null Conventional Logic (NCL) | |
| title.alternative | Defect-tolerant gate macro mapping and placement in clock-free nanowire crossbar architecture. | |
| title.alternative | Evaluation of defect-tolerant mapping and placement techniques for asynchronous crossbar architecture. | |
| contributor.advisor | Choi, Minsu | |
| contributor.author | Bonam, Ravi Kiran, 1985- | |
| subject | Null Conventional Logic (NCL) | |
| subject.LCSH | Asynchronous circuits. | |
| subject.LCSH | Logic circuits. | |
| subject.LCSH | Nanotechnology. | |
| subject.LCSH | Nanowires. | |
| date.issued | 2008 | |
| publisher | Missouri University of Science and Technology | |
| identifier.URI | ||
| identifier.citation | Bonam, Ravi. "Asynchronous Nanowire Crossbar Architecture for Manufacturability, Modularity and Robustness" Master's Thesis, Computer Engineering, Missouri University of Science and Technology, 2008. | |
| identifier.oclc | 226315154 | |
| description | Includes bibliographical references. | |
| description | Mode of access: World Wide Web. | |
| description | System requirements: Adobe Acrobat Reader; Internet browser. | |
| description | The entire thesis text is included in file. | |
| description | Thesis (M.S.)--Missouri University of Science and Technology, 2008. | |
| description | Title from title screen of thesis/dissertation PDF file (viewed April 28, 2008) | |
| description | Vita. | |
| description.abstract | "This thesis spotlights the dawn of a promising new nanowire crossbar architecture, the Asynchronous crossbar architecture, in the form of three different articles. It combines the reduced size of the nanowire crossbar architecture with the clock-free nature of Null Conventional Logic, which are the primary advantages. The first paper explains the proposed architecture with illustrations, including the design of an optimized full adder. This architecture has an elementary structure termed as a Programmable Gate Macro Block (PGMB) which is analogous to a threshold gate in NCL. The other two papers concentrate on mapping and placement techniques which are important due to defects involved in crossbars. These defects have to be tolerated and logic has to be routed appropriately for successful functioning of the circuit"--Introduction, p. [1]. | |
| description. statementOfResponsibility | by Ravi Kiron Bonam. | |
| type | Thesis/Dissertation | |
| type.DCMIType | text | |
| format.extent | x, 75 p. : ill., digital, PDF file. | |
| language.ISO639-2 | eng | |
| rights | These materials are protected under copyright by the original author. | |
| date.accessioned | 2008-04-09T19:50:57Z | |
| date.available | 2008-04-28T14:04:53Z | |
| identifier.persist.URI | ||
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