Scholars' Mine
Missouri S&T
Research Repository
Curtis Laws Wilson Library
400 W. 14th Street
Rolla, MO 65409-0060
scholarsmine@mst.edu
| Title: | A bipartite, differential I DDQ testable static RAM design | |
| Author (s): | Al-Assadi, Waleed K. Jayasumana, A.P. Malaiya, Y.K. | |
| Department/Lab Affiliations: | Electrical and Computer Engineering | |
| Keywords: | SRAM SRAM chips accuracy bipartite differential I/DDQ/ testable static RAM design current testing defect detection fault activation fault diagnosis fault location high-density IC fault detection integrated circuit testing memory partitioning off-line testing parallel write/read operations quiescent power supply current measurement static random access memories system operational speed test speed testability | |
| Issue Date: | 1995 | |
| Publisher: | Institute of Electrical and Electronics Engineers | |
| Citation: | Al-Assadi, W.K.; Jayasumana, A.P.; Malaiya, Y.K., "A bipartite, differential IDDQ testable static RAM design," Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing, 1995. pp.36-41, 7-8 Aug 1995 | |
| Abstract: | I DDQ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I DDQ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I DDQ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared | |
| Type: | Article - Conference proceedings text | |
| Copyright Notice: | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. FULL COPYRIGHT INFORMATION: | |
| Publisher URL: | ||
| Link to this page: | ||
| Full Text: |
|
| title | A bipartite, differential I DDQ testable static RAM design | |
| contributor.author | Al-Assadi, Waleed K. | |
| contributor.author | Jayasumana, A.P. | |
| contributor.author | Malaiya, Y.K. | |
| contributor.deptlab | Electrical and Computer Engineering | |
| subject | SRAM | |
| subject | SRAM chips | |
| subject | accuracy | |
| subject | bipartite differential I/DDQ/ testable static RAM design | |
| subject | current testing | |
| subject | defect detection | |
| subject | fault activation | |
| subject | fault diagnosis | |
| subject | fault location | |
| subject | high-density IC fault detection | |
| subject | integrated circuit testing | |
| subject | memory partitioning | |
| subject | off-line testing | |
| subject | parallel write/read operations | |
| subject | quiescent power supply current measurement | |
| subject | static random access memories | |
| subject | system operational speed | |
| subject | test speed | |
| subject | testability | |
| date.issued | 1995 | |
| date.submitted | 2007 | |
| publisher | Institute of Electrical and Electronics Engineers | |
| identifier.citation | Al-Assadi, W.K.; Jayasumana, A.P.; Malaiya, Y.K., "A bipartite, differential IDDQ testable static RAM design," Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing, 1995. pp.36-41, 7-8 Aug 1995 | |
| identifier.pub.URI | ||
| description.abstract | I DDQ (Defect Detection by Quiescent power supply current measurement), or current testing, has emerged in the last few years as an effective technique for detecting certain classes of faults in high-density ICs. In this paper, a testable design that enhances the I DDQ testability of static random access memories (SRAMs) for off-line testing as proposed. To achieve high accuracy and a test speed approaching the system operational speed, the memory is partitioned for comparison of I DDQ values. Parallel write/read operations are used to activate possible faults, while quiescent power supply currents from two blocks are compared | |
| type | Article - Conference proceedings | |
| type.DCMIType | text | |
| type.status | Final version | |
| rights | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | |
| rights.URI | ||
| date.accessioned | 2007-04-05T14:00:26Z | |
| date.available | 2007-04-05T14:00:25Z | |
| identifier.persist.URI | ||
| Full Text |
|