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| Title: | On fault modeling and testing of content-addressable memories | |
| Author (s): | Al-Assadi, Waleed K. Jayasumana, A.P. Malaiya, Y.K. | |
| Department/Lab Affiliations: | Electrical and Computer Engineering | |
| Keywords: | CAM architecture CAM chips IC testing associative memories content-addressable memories content-addressable storage fault diagnosis fault modeling integrated circuit testing integrated memory circuits memory architecture testing strategy | |
| Issue Date: | 1994 | |
| Publisher: | Institute of Electrical and Electronics Engineers | |
| Citation: | Al-Assadi, W.K.; Jayasumana, A.P.; Malaiya, Y.K., "On fault modeling and testing of content-addressable memories," Records of the IEEE International Workshop on Memory Technology, Design and Testing, 1994. pp.78-83, 8-9 Aug 1994 | |
| Abstract: | Associative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using the proposed fault model | |
| Type: | Article - Journal text | |
| Copyright Notice: | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. FULL COPYRIGHT INFORMATION: | |
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| title | On fault modeling and testing of content-addressable memories | |
| contributor.author | Al-Assadi, Waleed K. | |
| contributor.author | Jayasumana, A.P. | |
| contributor.author | Malaiya, Y.K. | |
| contributor.deptlab | Electrical and Computer Engineering | |
| subject | CAM architecture | |
| subject | CAM chips | |
| subject | IC testing | |
| subject | associative memories | |
| subject | content-addressable memories | |
| subject | content-addressable storage | |
| subject | fault diagnosis | |
| subject | fault modeling | |
| subject | integrated circuit testing | |
| subject | integrated memory circuits | |
| subject | memory architecture | |
| subject | testing strategy | |
| date.issued | 1994 | |
| date.submitted | 2007 | |
| publisher | Institute of Electrical and Electronics Engineers | |
| identifier.citation | Al-Assadi, W.K.; Jayasumana, A.P.; Malaiya, Y.K., "On fault modeling and testing of content-addressable memories," Records of the IEEE International Workshop on Memory Technology, Design and Testing, 1994. pp.78-83, 8-9 Aug 1994 | |
| identifier.pub.URI | ||
| description.abstract | Associative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using the proposed fault model | |
| type | Article - Journal | |
| type.DCMIType | text | |
| type.status | Final version | |
| rights | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | |
| rights.URI | ||
| date.accessioned | 2007-04-05T13:59:08Z | |
| date.available | 2007-04-05T13:59:08Z | |
| identifier.persist.URI | ||
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