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Title: On fault modeling and testing of content-addressable memories
Author (s): Al-Assadi, Waleed K.
Jayasumana, A.P.
Malaiya, Y.K.
Department/Lab Affiliations: Electrical and Computer Engineering
Keywords: CAM architecture
CAM chips
IC testing
associative memories
content-addressable memories
content-addressable storage
fault diagnosis
fault modeling
integrated circuit testing
integrated memory circuits
memory architecture
testing strategy
Issue Date: 1994
Publisher: Institute of Electrical and Electronics Engineers
Citation: Al-Assadi, W.K.; Jayasumana, A.P.; Malaiya, Y.K., "On fault modeling and testing of content-addressable memories," Records of the IEEE International Workshop on Memory Technology, Design and Testing, 1994. pp.78-83, 8-9 Aug 1994
Abstract: Associative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using the proposed fault model
Type: Article - Journal
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titleOn fault modeling and testing of content-addressable memories
contributor.authorAl-Assadi, Waleed K.
contributor.authorJayasumana, A.P.
contributor.authorMalaiya, Y.K.
contributor.deptlabElectrical and Computer Engineering
subjectCAM architecture
subjectCAM chips
subjectIC testing
subjectassociative memories
subjectcontent-addressable memories
subjectcontent-addressable storage
subjectfault diagnosis
subjectfault modeling
subjectintegrated circuit testing
subjectintegrated memory circuits
subjectmemory architecture
subjecttesting strategy
date.issued1994
date.submitted2007
publisherInstitute of Electrical and Electronics Engineers
identifier.citationAl-Assadi, W.K.; Jayasumana, A.P.; Malaiya, Y.K., "On fault modeling and testing of content-addressable memories," Records of the IEEE International Workshop on Memory Technology, Design and Testing, 1994. pp.78-83, 8-9 Aug 1994
identifier.pub.URI
http://ieeexplore.ieee.org/iel2/3170/8991/00397193.pdf?arnumber=39719
description.abstractAssociative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using the proposed fault model
typeArticle - Journal
type.DCMITypetext
type.statusFinal version
rightsThis material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
rights.URI
http://www.ieee.org/web/publications/rights/policies.html
date.accessioned2007-04-05T13:59:08Z
date.available2007-04-05T13:59:08Z
identifier.persist.URI
http://scholarsmine.mst.edu/post_prints/00397193_09007dcc8030bcf2.html
Full Text
00397193_09007dcc8030bcf7.pdf