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| Title: | Modeling of intra-cell defects in CMOS SRAM | |
| Author (s): | Al-Assadi, Waleed K. Malaiya, Y.K. Jayasumana, A.P. | |
| Department/Lab Affiliations: | Electrical and Computer Engineering | |
| Keywords: | CMOS SRAM CMOS integrated circuits IDDQ values SRAM chips bridging defects fault location fault models intercell coupling intra-cell defects semiconductor device models static random access memory stuck-on faults transistor stuck-open | |
| Issue Date: | 1993 | |
| Publisher: | Institute of Electrical and Electronics Engineers | |
| Citation: | Al-Assadi, W.K.; Malaiya, Y.K.; Jayasumana, A.P., "Modeling of intra-cell defects in CMOS SRAM," Records of the 1993 IEEE International Workshop on Memory Testing, pp.78-81, 9-10 Aug 1993 | |
| Abstract: | The effect of defects within a single cell of a static random access memory (SRAM) is examined. All major types of faults, including bridging, transistor stuck-open and stuck-on, are examined. A significant fraction of all faults cause high IDDQ values to be observed. Faults leading to inter-cell coupling are identified. | |
| Type: | Article - Conference proceedings text | |
| Copyright Notice: | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. FULL COPYRIGHT INFORMATION: | |
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| title | Modeling of intra-cell defects in CMOS SRAM | |
| contributor.author | Al-Assadi, Waleed K. | |
| contributor.author | Malaiya, Y.K. | |
| contributor.author | Jayasumana, A.P. | |
| contributor.deptlab | Electrical and Computer Engineering | |
| subject | CMOS SRAM | |
| subject | CMOS integrated circuits | |
| subject | IDDQ values | |
| subject | SRAM chips | |
| subject | bridging | |
| subject | defects | |
| subject | fault location | |
| subject | fault models | |
| subject | intercell coupling | |
| subject | intra-cell defects | |
| subject | semiconductor device models | |
| subject | static random access memory | |
| subject | stuck-on faults | |
| subject | transistor stuck-open | |
| date.issued | 1993 | |
| date.submitted | 2007 | |
| publisher | Institute of Electrical and Electronics Engineers | |
| identifier.citation | Al-Assadi, W.K.; Malaiya, Y.K.; Jayasumana, A.P., "Modeling of intra-cell defects in CMOS SRAM," Records of the 1993 IEEE International Workshop on Memory Testing, pp.78-81, 9-10 Aug 1993 | |
| identifier.pub.URI | ||
| description.abstract | The effect of defects within a single cell of a static random access memory (SRAM) is examined. All major types of faults, including bridging, transistor stuck-open and stuck-on, are examined. A significant fraction of all faults cause high IDDQ values to be observed. Faults leading to inter-cell coupling are identified. | |
| type | Article - Conference proceedings | |
| type.DCMIType | text | |
| type.status | Final version | |
| rights | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | |
| rights.URI | ||
| date.accessioned | 2007-04-05T13:57:25Z | |
| date.available | 2007-04-05T13:57:24Z | |
| identifier.persist.URI | ||
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