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| Title: | Faulty behavior of storage elements and its effects on sequential circuits | |
| Author (s): | Al-Assadi, Waleed K. Malaiya, Y.K. Jayasumana, A.P. | |
| Department/Lab Affiliations: | Electrical and Computer Engineering | |
| Keywords: | clock-feedthrough behavior data-feedthrough behavior fault behaviors fault coverage fault detectability fault location fault model logic level retention logic testing physical failures sequential circuits storage elements transistor-level faults | |
| Issue Date: | 1993 | |
| Publisher: | Institute of Electrical and Electronics Engineers | |
| Citation: | Al-Assadi, W.K.; Malaiya, Y.K.; Jayasumana, A.P., "Faulty behavior of storage elements and its effects on sequential circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.1, no.4 pp.446-452, Dec 1993 | |
| Abstract: | It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault model. These include data-feedthrough and clock-feedthrough behaviors, as well as problems with logic level retention. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit. The detectability of feedthrough faults is considered. | |
| Type: | Article - Journal text | |
| Copyright Notice: | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. FULL COPYRIGHT INFORMATION: | |
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| title | Faulty behavior of storage elements and its effects on sequential circuits | |
| contributor.author | Al-Assadi, Waleed K. | |
| contributor.author | Malaiya, Y.K. | |
| contributor.author | Jayasumana, A.P. | |
| contributor.deptlab | Electrical and Computer Engineering | |
| subject | clock-feedthrough behavior | |
| subject | data-feedthrough behavior | |
| subject | fault behaviors | |
| subject | fault coverage | |
| subject | fault detectability | |
| subject | fault location | |
| subject | fault model | |
| subject | logic level retention | |
| subject | logic testing | |
| subject | physical failures | |
| subject | sequential circuits | |
| subject | storage elements | |
| subject | transistor-level faults | |
| date.issued | 1993 | |
| date.submitted | 2007 | |
| publisher | Institute of Electrical and Electronics Engineers | |
| identifier.citation | Al-Assadi, W.K.; Malaiya, Y.K.; Jayasumana, A.P., "Faulty behavior of storage elements and its effects on sequential circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.1, no.4 pp.446-452, Dec 1993 | |
| identifier.issn | 1063-8210 | |
| identifier.pub.URI | ||
| description.abstract | It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault model. These include data-feedthrough and clock-feedthrough behaviors, as well as problems with logic level retention. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit. The detectability of feedthrough faults is considered. | |
| type | Article - Journal | |
| type.DCMIType | text | |
| type.status | Final version | |
| rights | This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | |
| rights.URI | ||
| date.accessioned | 2007-04-05T13:57:13Z | |
| date.available | 2007-04-05T13:57:13Z | |
| identifier.persist.URI | ||
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