Fault modeling and testability of domino CMOS logic
"Domino CMOS circuits are widely used in high performance integrated circuits due to their advantages of speed, area, and power consumption over other logic families. However, testing of domino circuits is an area which still requires considerable attention. In this thesis two aspects of testing domino circuits are investigated. First, the effectiveness of popular fault models in detecting defects in domino circuits is studied. A design-for-test scheme targeted towards undetected faults is proposed and the feasibility of the scheme is proven. The second aspect that is examined is crosstalk due to capacitive circuit noise immunity in terms of signal switching speed and coupling capacitance. The validity of the model is demonstrated using SPICE simulations"--Abstract, leaf iii.
Electrical and Computer Engineering
M.S. in Computer Engineering
University of Missouri--Rolla
ix, 57 leaves
© 2006 Pavankumar Chandrasekhar, All rights reserved.
Thesis - Citation
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary
Electronic circuits -- Noise
Crosstalk -- Prevention
Print OCLC #
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.http://laurel.lso.missouri.edu/record=b6432174~S5
Chandrasekhar, Pavankumar, "Fault modeling and testability of domino CMOS logic" (2006). Masters Theses. 5864.