"This paper describes the organization and failure analysis of various types of binary address decoders. Logical type faults are considered and all possible faulty output patterns, resulting from these faults, are derived. A basic theory is developed, showing that these failure patterns are independent of the decoder size and organization. Digital simulation programs were used as an aid in the development of this theory. Results of the simulation are provided in the appendix"--Abstract, page ii.
Szygenda, Stephen A.
Tracey, James H.
Ho, C. Y. (Chung You), 1933-1988
Electrical and Computer Engineering
M.S. in Electrical Engineering
University of Missouri--Rolla
vi, 118 pages
© 1969 Kanaiyalal Jekisondas Gandhi, All rights reserved.
Thesis - Open Access
Library of Congress Subject Headings
Failure time data analysis
Binary system (Mathematics)
Signal theory (Telecommunication)
Print OCLC #
Electronic OCLC #
Link to Catalog Recordhttp://laurel.lso.missouri.edu/record=b2614145~S5
Gandhi, Kanaiyalal Jekisondas, "Failure analysis of binary address decoders" (1969). Masters Theses. 5354.