The analysis of a phase-locked loop by the functional expansion method

Author

Hugh Francis Spence

Abstract

"The time response of a generalized second order Phase-Locked Loop to step and ramp inputs is described by a functional power, truncated at the third order term. The responses given by the functional power series differs from the analog simulation by less than 6% when the inputs are below 2.0 rad (rad/sec)"--Abstract, page ii.

Advisor(s)

Kern, Frank J.

Committee Member(s)

Wright, F. T.
Bertnolli, Edward C.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Electrical Engineering

Publisher

University of Missouri at Rolla

Publication Date

1968

Pagination

viii, 59 pages

Note about bibliography

Includes bibliographical references (page 68).

Rights

© 1968 Hugh F. Spence, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Subject Headings

Electronic circuit design
Phase-locked loops
Synchronous data transmission systems

Thesis Number

T 2081

Print OCLC #

5994908

Electronic OCLC #

802291209

Link to Catalog Record

http://merlin.lib.umsystem.edu/record=b1067789~S5

Recommended Citation

Spence, Hugh Francis, "The analysis of a phase-locked loop by the functional expansion method" (1968). Masters Theses. 5220.
https://scholarsmine.mst.edu/masters_theses/5220