Keywords and Phrases
Null Conventional Logic (NCL)
"This thesis spotlights the dawn of a promising new nanowire crossbar architecture, the Asynchronous crossbar architecture, in the form of three different articles. It combines the reduced size of the nanowire crossbar architecture with the clock-free nature of Null Conventional Logic, which are the primary advantages. The first paper explains the proposed architecture with illustrations, including the design of an optimized full adder. This architecture has an elementary structure termed as a Programmable Gate Macro Block (PGMB) which is analogous to a threshold gate in NCL. The other two papers concentrate on mapping and placement techniques which are important due to defects involved in crossbars. These defects have to be tolerated and logic has to be routed appropriately for successful functioning of the circuit"--Introduction, page 1.
McCracken, Theodore E.
Al-Assadi, Waleed K.
Electrical and Computer Engineering
M.S. in Computer Engineering
Missouri University of Science and Technology
Journal article titles appearing in thesis/dissertation
- Clock-free nanowire crossbar architecture based on Null Conventional Logic (NCL)
- Defect-tolerant gate macro mapping and placement in clock-free nanowire crossbar architecture
- Evaluation of defect-tolerant mapping and placement techniques for asynchronous crossbar architecture
x, 75 pages
© 2008 Ravi Kiron Bonam, All rights reserved.
Thesis - Open Access
Library of Congress Subject Headings
Print OCLC #
Electronic OCLC #
Link to Catalog Record
Bonam, Ravi, "Asynchronous nanowire crossbar architecture for manufacturability, modularity and robustness" (2008). Masters Theses. 4607.