Masters Theses

Author

Ravi Bonam

Keywords and Phrases

Null Conventional Logic (NCL)

Abstract

"This thesis spotlights the dawn of a promising new nanowire crossbar architecture, the Asynchronous crossbar architecture, in the form of three different articles. It combines the reduced size of the nanowire crossbar architecture with the clock-free nature of Null Conventional Logic, which are the primary advantages. The first paper explains the proposed architecture with illustrations, including the design of an optimized full adder. This architecture has an elementary structure termed as a Programmable Gate Macro Block (PGMB) which is analogous to a threshold gate in NCL. The other two papers concentrate on mapping and placement techniques which are important due to defects involved in crossbars. These defects have to be tolerated and logic has to be routed appropriately for successful functioning of the circuit"--Introduction, page 1.

Advisor(s)

Choi, Minsu

Committee Member(s)

McCracken, Theodore E.
Al-Assadi, Waleed K.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Publisher

Missouri University of Science and Technology

Publication Date

Spring 2008

Journal article titles appearing in thesis/dissertation

  • Clock-free nanowire crossbar architecture based on Null Conventional Logic (NCL)
  • Defect-tolerant gate macro mapping and placement in clock-free nanowire crossbar architecture
  • Evaluation of defect-tolerant mapping and placement techniques for asynchronous crossbar architecture

Pagination

x, 75 pages

Note about bibliography

Includes bibliographical references (pages 56-58) and index (pages 59-61).

Rights

© 2008 Ravi Kiron Bonam, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Library of Congress Subject Headings

Asynchronous circuits
Logic circuits
Nanotechnology
Nanowires

Thesis Number

T 9342

Print OCLC #

260034075

Electronic OCLC #

226315154

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