Masters Theses

Keywords and Phrases

Chemically-Assembled Electronic Nanotechnology (CAEN)

Abstract

"Nanotechnology has been shown to have the potential to replace the existing CMOS technology in the race to maintain the Moore's Law increases in IC complexity. This work considers the Chemically Assembled Electronic Nanotechnology (CAEN), which fabricates nanofabric using a low cost self-assembly and self-alignment chemical process and provides very high density. However, the main disadvantage of this technology is the inherently high defect rate that hinders the efforts to commercialize such systems. Existing testing and design techniques, for example for FPGAs, are ill suited since they typically assume vary low defect rates.

This thesis is comprised of two papers. In the paper I, a novel testing methodology is proposed along with a new set of test patterns and configurations which test the entire nanofabric for stuck-at, bridging and cross-point faults. An optimization technique is described to reduce the number of test configurations and testing time. A customization technique is also discussed to further increase the yield of the nanofabric when the desired functionality is known. Once the nanofabric has been tested and the faulty areas in the chip have been identified, the next step is to map the logic onto the nanofabric. The paper II discusses a new logic mapping approach for nanofabrics which have been tested to successfully implement AND/OR configurations of various logic functions. This approach uses the information provided by the testing technique from the paper I to simplify the logic mapping process. It used standard implementations of nanoblocks as compared to the existing techniques, which require customized solutions"--Abstract, page iv.

Advisor(s)

Zawodniok, Maciej Jan, 1975-

Committee Member(s)

Beetner, Daryl G.
Choi, Minsu

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Publisher

Missouri University of Science and Technology

Publication Date

Fall 2011

Journal article titles appearing in thesis/dissertation

  • Optimized testing technique for defect tolerance in CAEN-based nanofabric systems
  • Introduction to a novel defect-aware logic mapping approach for crossbar-based nanofabrics

Pagination

xi, 73 pages

Note about bibliography

Includes bibliographical references.

Rights

© 2011 Sambhav Dilip Kundaikar, All rights reserved.

Document Type

Thesis - Restricted Access

File Type

text

Language

English

Library of Congress Subject Headings

Fault tolerance (Engineering)
Mathematical optimization
Nanofibers
Nanostructured materials
Nanotechnology

Thesis Number

T 9932

Print OCLC #

795516413

Electronic OCLC #

909291178

Link to Catalog Record

Electronic access to the full-text of this document is restricted to Missouri S&T users. Otherwise, request this publication directly from Missouri S&T Library or contact your local library.

http://laurel.lso.missouri.edu/record=b8625329~S5

Comments

A condensed version of Paper I titled "Optimized built-in self-test technique for CAEN-based nanofabric systems" has been accepted at the IEEE NANO 2011, to be held in Portland-Oregon, August 15-19,2011.

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