An asynchronous FPGA for NULL Convention Logic circuits

Author

Arun Swaminathan Balasubramanian

Keywords and Phrases

NULL Convention Logic circuits; Look-up tables

Abstract

"This Master's thesis is intended to familiarize the reader with the asynchronous delay-insensitive NULL convention Logic (NCL) paradigm and illustrate the design of a completely asynchronous Field Programmable Gate Array (FPGA) for NULL Convention Logic circuits. Mentor Graphics Design Automation tools such as Design Architect and Accusim II were extensively used in creating this design"--Introduction, page 1.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Publisher

University of Missouri--Rolla

Publication Date

Spring 2005

Pagination

ix, 77 pages

Rights

© 2005 Arun Balasubramanian, All rights reserved.

Document Type

Thesis - Citation

File Type

text

Language

English

Subject Headings

Field programmable gate arrays -- Design and construction
Logic circuits -- Design and construction

Thesis Number

T 8807

Print OCLC #

63171514

Link to Catalog Record

Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.

Recommended Citation

Balasubramanian, Arun Swaminathan, "An asynchronous FPGA for NULL Convention Logic circuits" (2005). Masters Theses. 3745.
https://scholarsmine.mst.edu/masters_theses/3745