Masters Theses

Title

Using a VHDL testbench for transistor-level simulation and power calculation of NULL convention asynchronous digital circuits

Author

Anshul Singh

Abstract

"This thesis focuses on describing the method for simulating transistor-level design with a VHDL testbench and calculation of the average power per operation for NULL Convention Logic (NCL) asynchronous delay-insensitive digital circuits, using one of the industry standard "synchronous" design tool suites, Mentor Graphics"--Abstract, leaf iii.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Electrical Engineering

Publisher

University of Missouri--Rolla

Publication Date

Fall 2004

Pagination

viii, 73 leaves

Note about bibliography

Includes bibliographical references.

Rights

© 2004 Anshul Singh, All rights reserved.

Document Type

Thesis - Citation

File Type

text

Language

English

Library of Congress Subject Headings

VHDL (Computer hardware description language)
Logic design
Logic, Symbolic and mathematical
Transistor circuits -- Simulation methods

Thesis Number

T 8688

Print OCLC #

62080451

Link to Catalog Record

Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.

http://laurel.lso.missouri.edu/record=b5371316~S5

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