Using a VHDL testbench for transistor-level simulation and power calculation of NULL convention asynchronous digital circuits
"This thesis focuses on describing the method for simulating transistor-level design with a VHDL testbench and calculation of the average power per operation for NULL Convention Logic (NCL) asynchronous delay-insensitive digital circuits, using one of the industry standard "synchronous" design tool suites, Mentor Graphics"--Abstract, leaf iii.
Electrical and Computer Engineering
M.S. in Electrical Engineering
University of Missouri--Rolla
viii, 73 leaves
© 2004 Anshul Singh, All rights reserved.
Thesis - Citation
Library of Congress Subject Headings
VHDL (Computer hardware description language)
Logic, Symbolic and mathematical
Transistor circuits -- Simulation methods
Print OCLC #
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.http://laurel.lso.missouri.edu/record=b5371316~S5
Singh, Anshul, "Using a VHDL testbench for transistor-level simulation and power calculation of NULL convention asynchronous digital circuits" (2004). Masters Theses. 3612.