Using a VHDL testbench for transistor-level simulation and power calculation of NULL convention asynchronous digital circuits
"This thesis focuses on describing the method for simulating transistor-level design with a VHDL testbench and calculation of the average power per operation for NULL Convention Logic (NCL) asynchronous delay-insensitive digital circuits, using one of the industry standard "synchronous" design tool suites, Mentor Graphics"--Abstract, leaf iii.
Electrical and Computer Engineering
M.S. in Electrical Engineering
University of Missouri--Rolla
viii, 73 leaves
© 2004 Anshul Singh, All rights reserved.
Thesis - Citation
Library of Congress Subject Headings
VHDL (Computer hardware description language)
Logic, Symbolic and mathematical
Transistor circuits -- Simulation methods
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Link to Catalog Record
Singh, Anshul, "Using a VHDL testbench for transistor-level simulation and power calculation of NULL convention asynchronous digital circuits" (2004). Masters Theses. 3612.
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