Masters Theses

Title

Design and characterization of asynchronous delay-insensitive arithmetic components using NULL conventional logic

Keywords and Phrases

NULL Convention Logic (NCL)

Abstract

"This thesis focuses on design and characterization of arithemetic circuits, such as multipliers and ALUs, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to aid in the integration of asynchronous design paradigms, like NCL, into the semiconductor design industry."--Abstract, page iii.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Publisher

University of Missouri--Rolla

Publication Date

Summer 2003

Pagination

x, 67 leaves

Note about bibliography

Includes bibliographical references (leaves 113-121).

Rights

© 2003 Satish Kumar Bandapati, All rights reserved.

Document Type

Thesis - Citation

File Type

text

Language

English

Library of Congress Subject Headings

Computer arithmetic and logic units
Computer programming
Logic circuits

Thesis Number

T 8439

Print OCLC #

55232239

Link to Catalog Record

Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.

http://laurel.lso.missouri.edu/record=b5089517~S5

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