Design and Implementation of FPGA Configuration Logic Block using Asynchronous Semi-Static NCL Circuits
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This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-static NULL convention logic (NCL) Library. The proposed design uses three semi-static LLT's for implementing NCL logic functions. Each LLT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and Operation mode. The Static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.