Modeling Multilayered PCB Power-Bus Designs using an MPIE Based Circuit Extraction Technique
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Abstract
A circuit extraction tool (CEMPIE) has been developed based on the mixed-potential integral equation (MPIE) using a quasi-static approximation. A power-bus in a multi-layered PCB consisting of a pair of dedicated ground and power planes is studied using this tool. The distributed behavior of a power-bus is represented by a collection of passive circuit elements, which is valid up to several gigahertz. The decoupling performance of a power-bus due to its layer spacing and the dielectric constant is evaluated for simple test geometries. The impact of the relative distance between the noise source and the potential receiver is also studied. Novel structures such as a power island were studied in both thin and thick boards, and the decoupling performance due to the locations and values of the decoupling capacitors were also investigated
