Implementation of Static and Semi-Static Versions of a Bit-wise Pipelined Dual-rail NCL 2S Complement Multiplier
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Abstract
This paper focuses on implementing a 2s complement 8x8 dual-rail bit-wise pipelined multiplier using the asynchronous NULL Convention Logic (NCL) paradigm. The design utilizes a Wallace tree for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8V 0.18,um TSMC CMOS process.The multiplier is realized using both static and semi-static Dualversions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.
This paper has been withdrawn.
