Modeling of Intra-Cell Defects in CMOS SRAM

Waleed K. Al-Assadi, Missouri University of Science and Technology
Y. K. Malaiya
A. P. Jayasumana

This document has been relocated to http://scholarsmine.mst.edu/ele_comeng_facwork/1146

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Abstract

The effect of defects within a single cell of a static random access memory (SRAM) is examined. All major types of faults, including bridging, transistor stuck-open and stuck-on, are examined. A significant fraction of all faults cause high IDDQ values to be observed. Faults leading to inter-cell coupling are identified.