Recently, we proposed a new clock-free nanowire crossbar architecture based on a delayinsensitive paradigm called Null Convention Logic (NCL). The proposed architecture has simple periodic structure that is suitable for non-deterministic nanoscale assembly and does not require a clock distribution network - so it is intrinsically free from timing-related failure modes. Even though the proposed architecture offers improved manufacturability, it is still not free from defects. This paper elaborates on the different programming techniques to map a given threshold gate macro on a random PGMB (Programmable Gate Macro Block) with predefined dimension. Defect-Aware and Defect Unaware approaches have been considered to map a given threshold gate onto a PGMB without affecting its functionality. Defect aware approach uses a defect map, gate table which help in efficient programming and also conservative use of resources. Defect unaware approach on the other hand is faster than defect aware approach, does not use defect maps and is not as efficient as defect aware approach. Parametric simulation results using MATLAB are used to show the programmability of these approaches under various circumstances.
R. Bonam et al., "Defect-Tolerant Gate Macro Mapping & Placement in Clock-free Nanowire Crossbar Architecture," Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, 2007, Institute of Electrical and Electronics Engineers (IEEE), Jan 2007.
The definitive version is available at http://dx.doi.org/10.1109/DFT.2007.62
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, 2007
Electrical and Computer Engineering
Keywords and Phrases
Circuit Layout; Fault Tolerance; Logic circuits; Nanowires
Article - Conference proceedings
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