Title

Analysis and Simulation of Jitter for High Speed Channels in VLSI Systems

Abstract

This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigabit per second) IO channels in VLSI systems). Jitter components are analyzed and modeled individually. The unique features of the components when they are simultaneously injected are identified through simulation. In this work, the effect of settling time on ISI and the relationship among each jitter component are investigated in depth. The validity of superposition of the jitter components is confirmed.

Meeting Name

IEEE Instrumentation and Measurement Technology Conference: IMTC: Synergy of Science and Technology in Instrumentation and Measurement (2007: May 1-3, Warsaw, Poland)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Duty Cycle Distortion; Inter-Symbol Interference; Jitter Components; Serial Data Systems; Timing Jitter; Periodic Jitter; Random Jitter; Channel Estimation; Computer Simulation; Input Output Programs; Intersymbol Interference; Velocity Measurement; VLSI Circuits; Jitter

International Standard Book Number (ISBN)

1424405882

International Standard Serial Number (ISSN)

1091-5281

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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