Analysis and Simulation of Jitter for High Speed Channels in VLSI Systems
This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigabit per second) IO channels in VLSI systems). Jitter components are analyzed and modeled individually. The unique features of the components when they are simultaneously injected are identified through simulation. In this work, the effect of settling time on ISI and the relationship among each jitter component are investigated in depth. The validity of superposition of the jitter components is confirmed.
K. K. Kim et al., "Analysis and Simulation of Jitter for High Speed Channels in VLSI Systems," Proceedings of the IEEE Instrumentation and Measurement Technology Conference: Synergy of Science and Technology in Measurement (2007, Warsaw, Poland), Institute of Electrical and Electronics Engineers (IEEE), May 2007.
The definitive version is available at http://dx.doi.org/10.1109/IMTC.2007.379345
IEEE Instrumentation and Measurement Technology Conference: IMTC: Synergy of Science and Technology in Instrumentation and Measurement (2007: May 1-3, Warsaw, Poland)
Electrical and Computer Engineering
Keywords and Phrases
Duty Cycle Distortion; Inter-Symbol Interference; Jitter Components; Serial Data Systems; Timing Jitter; Periodic Jitter; Random Jitter; Channel Estimation; Computer Simulation; Input Output Programs; Intersymbol Interference; Velocity Measurement; VLSI Circuits; Jitter
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International Standard Serial Number (ISSN)
Article - Conference proceedings
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