In this work, we use static and semi-static versions of NULL Convention Logic (NCL) primitives (i.e., threshold gates) to implement a dual-rail 8times8 2s complement multiplier using the Modified Booth2 algorithm for partial product generation and a Wallace tree for partial product summation. We establish the multiplier's functionality utilizing VHDL-based simulations of the gate-level structural design. The design is then implemented at the transistor-level and layout-level using both static and semi-static threshold gates, for a 1.8V 0.18mum TSMC CMOS process; and these two implementations are compared in terms of area, power, and speed.
M. V. Joshi et al., "NCL Implementation of Dual-Rail 2S Complement 8Ã8 Booth2 Multiplier using Static and Semi-Static Primitives," Proceedings of the IEEE Region 5 Technical Conference, 2007, Institute of Electrical and Electronics Engineers (IEEE), Apr 2007.
The definitive version is available at http://dx.doi.org/10.1109/TPSD.2007.4380352
IEEE Region 5 Technical Conference, 2007
Electrical and Computer Engineering
National Science Foundation (U.S.)
Keywords and Phrases
CMOS Logic Cicuits; NCL; NULL Convention Logic; Cicuit Simulation; Hardware Description Languages; Logic Design; Multiplying Circuits; Threshold Logic
Library of Congress Subject Headings
Metal oxide semiconductors, Complementary
VHDL (Computer hardware description language)
Article - Conference proceedings
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