Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents.
K. K. Kim et al., "Leakage Minimization Technique for Nanoscale CMOS VLSI," IEEE Design & Test of Computers, Institute of Electrical and Electronics Engineers (IEEE), Jan 2007.
The definitive version is available at http://dx.doi.org/10.1109/MDT.2007.111
Electrical and Computer Engineering
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