Design and Characterization of NULL Convention Arithmetic Logic Units
In this paper, a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using the delay-insensitive NULL convention logic paradigm, and are characterized in terms of speed and area. Both dual-rail and quad-rail, pipelined and non-pipelined versions are developed, and the tradeoffs and design considerations for each are discussed. Comparing the various architectures shows that the fastest dual-rail and quad-rail ALUs achieve average speedups of 1.72 and 1.59, respectively, over their non-pipelined counterparts, while requiring 133% and 119% more area, respectively. Overall, the dual-rail designs are both faster and require less area than their respective quad-rail counterparts; however, the quad-rail versions are expected to consume less power.
S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," Microelectronic Engineering, Elsevier, Jan 2007.
The definitive version is available at http://dx.doi.org/10.1016/j.mee.2006.02.012
Electrical and Computer Engineering
Keywords and Phrases
Arithmetic Logic Unit; Asynchronous Logic Design; Delay-Insensitive Circuits; Self-Timed Circuits
Library of Congress Subject Headings
Article - Journal
© 2007 Elsevier, All rights reserved.