Title

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Abstract

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

ATPG; NULL Convention Logic (NCL); SCOAP; Design for Test (DFT)

Library of Congress Subject Headings

Asynchronous circuits

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2009 Springer-Verlag, All rights reserved.


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