Title

Design for Test Methodology for the IBM PowerPC™ 440 Embedded Core

Abstract

This paper presents a Design-for-Test (DFT) methodology for the IBM PowerPC™ 440 embedded processors implemented in 130 nm technology. The paper discusses highlights of the DFT techniques that address challenges of achieving highly testable and debuggable product. The paper addresses enhancements of debugging by providing better tracking of initial silicon capabilities for improved yield and time-to-market.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

BIST; Design for Test (DFT); IBM; PowerPC; Microprocessors; Scan

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2005 CSREA Press, All rights reserved.

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