An Adaptive VLSI Neural Network Chip
Presents an adaptive neural network, which uses multiplying-digital-to-analog converters (MDACs) as synaptic weights. The chip takes advantage of digital processing to learn weights, but retains the parallel asynchronous behavior of analog systems, since part of the neuron functions are analog. The authors use MDAC units of 6 bit accuracy for this chip. Hebbian learning is employed, which is very attractive for electronic neural networks since it only uses local information in adapting weights.
R. Zaman and D. C. Wunsch, "An Adaptive VLSI Neural Network Chip," Neural Networks, 1994. IEEE World Congress on Computational Intelligence, 1994 International Conference on Neural Networks (ICNN'94), vol. 4, pp. 2018-2021, Institute of Electrical and Electronics Engineers (IEEE), Jan 1994.
The definitive version is available at http://dx.doi.org/10.1109/ICNN.1994.374523
1994 IEEE International Conference on Neural Networks (ICNN'94)- 1st IEEE World Congress on Computational Intelligence (1994: Jun. 27-Jul. 2, Orlando, FL)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
Article - Conference proceedings
© 1994 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.