Title

Impact of Chip and Interposer PDN to Eye Diagram in High Speed Channels

Abstract

The paper applies the combined SI-PI co-simulation to on chip high speed interconnects. A complete model of chip and interposer PDN is developed and, together to a lumped model of the PCB and package PDN, it is employed to supply I/O drivers for HBM traces laid out on silicon interposer. A comprehensive analysis is carried out highlighting the impact of the decoupling capacitor placement and their corresponding parasitic inductance on the supply voltage ripple and on the output eye diagram at the signal receivers.

Meeting Name

22nd IEEE Workshop on Signal and Power Integrity, SPI (2018: May 22-25, Brest, France)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Polychlorinated biphenyls; Silicon compounds; Voltage control; Co-simulations; Decoupling capacitor; Eye diagrams; High bandwidth; Power distribution network; Signal receivers; Decoupling capacitors; Eye diagram; High bandwidth memory; Power distribution network; SI-PI co-simulation

International Standard Book Number (ISBN)

978-1-5386-2299-5

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2018 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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