Abstract

Two-dimensional simulations of amorphous silicon thin-film transistors are presented for the case when source-drain voltage is turned on long before gate voltage is turned on. Discrepancies between these results and the one-dimensional results of M. F. Willums, M. Hack, P. G. LeComber, and J. G. Shaw [MRS Symp. Proc. 258, 985 (1992)] are discussed. Valid reasons for drain current decay are provided, and occupation dynamics for the trap states are shown in order to distinguish these from the one-dimensional results of C. van Berkel, J. R. Hughes, and M. J. Powell [J. Appl. Phys. 66, 4488 (1989)] where a two-fluid model occupation function was assumed. The invalidity of such approximation is explicitly demonstrated. The mean trap-filling energy level moves up in three stages: First, the level varies with log t, then varies linearly with t, and finally, with log (log t) to a steady-state level.

Department(s)

Electrical and Computer Engineering

International Standard Serial Number (ISSN)

0021-8979

Document Type

Article - Journal

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 1994 American Institute of Physics (AIP), All rights reserved.

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