Regressive Testing for System-on-Chip with Unknown-Good-Yield
Abstract
This paper presents a testing method for electronic devices with no a-priori yield information. This problem is referred to as Unknown-Good-Yield (UKGY) problem. The UKGY problem of Systems-on-Chip (SoC) is discussed in this paper as SoCs are in general built with embedded Intellectual Property (IP) Cores, each of which procured from IP providers with no information on Known-Good-Yield (KGY). In general, partial testing is a practical choice for assuring the yield of the product under the stringent time-to-market requirement in today's high density/complexity electronic devices such as SoC built with deep submicron or nano technology. Therefore, efficient and effective sampling technique is a key to the success of high confidence testing. An Experimental Characterization-based Testing (referred to as ET) method for SoC has been proposed prior to this work, in which a stratified sampling method was employed based on environmental-based characterization and experimental design technique to enhance the confidence level of the estimation of yield. The proposed testing method, referred to as Regressive Testing (RegT), in this paper exploits another way around by using parameters (referred to as Assistant Variables (AV) free from UKGY that determines the criteria to sample and test SoCs, and employs the regression analysis method to evaluate the yield with regard to confidence interval. A numerical simulation is conducted to demonstrate the efficiency and effectiveness of the proposed RegT in comparison with generic random testing method.
Recommended Citation
N. J. Park et al., "Regressive Testing for System-on-Chip with Unknown-Good-Yield," Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2003, Boston, MA), pp. 393 - 400, IEEE Computer Society, Nov 2003.
The definitive version is available at https://doi.org/10.1109/DFTVS.2003.1250136
Meeting Name
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2003: Nov. 3-5, Boston, MA)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Application Specific Integrated Circuits; Defects; Design for Testability; Electronic Equipment; Embedded Systems; Fault Tolerance; Numerical Methods; Programmable Logic Controllers; Regression Analysis; Thermoelectric Equipment; Confidence Interval; Electronic Device; Experimental Characterization; Experimental Design Techniques; Intellectual Property Cores; Regression Analysis Methods; Sampling Technique; Stratified Sampling; System-on-Chip
International Standard Book Number (ISBN)
769520421
International Standard Serial Number (ISSN)
1550-5774
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2003 IEEE Computer Society, All rights reserved.
Publication Date
01 Nov 2003
