Performance Assessment of Analog Circuits with Carbon Nanotube FET (CNFET)

Abstract

Carbon Nanotube FET technology is a new promising technology for high speed digital applications. This paper investigates optimizing analog circuits architecture to take advantage of this technology in mixed mode ICs. It was found through simulations that the optimum topology for high-bandwidth analog circuits is obtained by using an architecture which avoids loading by the high CNFET gate capacitance in the main signal path at high impedance points. Low junction capacitances of CNFET and high transconductance (gm) compared to silicon MOSFET indicates that high gain-bandwidth can be obtained by using CNFET. Simulations indicate low voltage operation (0.5 V) is possible using CNFET technology and also high temperature operation ( > 200 C) is possible. Monte-Carlo simulations indicate that device matching of important CNFET parameters such as nanotube diameter, channel length, source/drain doping are important to get consistent results.

Meeting Name

20th Great Lakes Symposium on VLSI: GLSVLSI (2010: May 16-18, Providence, RI)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Analog; Carbon Nanotube FET; Channel Length; Digital Applications; Gate Capacitance; High Bandwidth; High Gain; High Impedance; Junction Capacitances; Low Voltage Operation; Mixed Mode; Monte Carlo Simulation; Nanotube Diameters; Optimum Topologies; Performance Assessment; Signal Paths; Silicon MOSFET; Capacitance; Carbon Nanotubes; High Temperature Operations; Lakes; MESFET Devices; Semiconducting Silicon Compounds; Technology; Analog Circuits; Circuits

International Standard Book Number (ISBN)

978-1450300124

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2010 Association for Computing Machinery (ACM), All rights reserved.

Publication Date

01 May 2010

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