Offset Voltage Analysis of Dynamic Latched Comparator
The offset voltage of the dynamic latched comparator is analyzed in detail, and the dynamic latched comparator design is optimized for the minimal offset voltage based on the analysis in this paper. As a result, 1-sigma offset voltage was reduced from 12.5mV to 6.5mV at the cost of 9% increase of the power dissipation (152μW from 136μW). Using a digitally controlled capacitive offset calibration technique, the offset voltage of the comparator is further reduced from 6.50mV to 1.10mV at 1-sigma at the operating clock frequency of 3 GHz and it consumes 54μW/GHz after the calibration.
H. Jeon et al., "Offset Voltage Analysis of Dynamic Latched Comparator," Proceedings of the IEEE 54th International Midwest Symposium on Circuits and Systems (2011, Seoul, South Korea), Institute of Electrical and Electronics Engineers (IEEE), Aug 2011.
The definitive version is available at https://doi.org/10.1109/MWSCAS.2011.6026358
IEEE 54th International Midwest Symposium on Circuits and Systems: MWSCAS (2011: Aug. 7-10, Seoul, South Korea)
Electrical and Computer Engineering
Keywords and Phrases
Clock Frequency; Offset Calibration; Offset Voltage; Calibration; Comparator Circuits; Comparators (Optical); Electric Network Analysis; Dynamic Analysis
International Standard Book Number (ISBN)
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Article - Conference proceedings
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