Title

Multi-Stage BCH Decoder to Mitigate Hotspot-Induced Bit Error Variation

Abstract

3D heterogeneous integration (commonly termed as 3DIC) of CPU, GPU and DRAM dies vertically interconnected by a massive number of TSVs (Through-Silicon Vias) is expected to overcome limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability in temperature (i.e., hotspots) is anticipated to result in bit error variation in DRAM die. A novel multi-stage BCH decoder has been proposed to efficiently address this issue in this work. The proposed multi-stage BCH decoder is designed to tolerate up to a certain maximum number of error bits per codeword, which is estimated from the on-line thermal gradient data, to minimize the decoding latency.

Meeting Name

Proceedings of the International SoC Design Conference: ISOCC: SoC for Internet of Everything (IoE) (2015: Nov. 2-5, Gyeongju, South Korea)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Decoding; Electronics Packaging; Energy Utilization; Errors; Integrated Circuit Interconnects; Programmable Logic Controllers; 3D Heterogeneous Integration; BCH Decoders; Bit-Errors; Hotspots; Limited Bandwidth; Multi Stage; Spatial and Temporal Variability; Through Silicon Vias; Three Dimensional Integrated Circuits

International Standard Book Number (ISBN)

9781467393089

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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