Title

Modulo 2n + 1 squarer design for efficient hardware implementation

Abstract

In this work, an efficient hardware architecture of modulo 2n + 1 squarer is proposed and validated. The proposed modulo 2n + 1 squarer use novel compressor designs and sparse tree adders as primitive building blocks for fast low-power operations in three major functional modules including partial products generation module, partial products reduction module and final stage addition module. The resulting modulo 2n + 1 squarer has been implemented in standard CMOS (Complementary Metal-Oxide Semiconductor) cell technology and compared both qualitatively and quantitatively with the existing hardware implementations. The unit gate model analysis and the experimental results show that the proposed implementation is faster and consume less power than existing hardware implementations.

Meeting Name

International SoC Design Conference: ISOCC (2014: Nov. 3-6, Jeju, South Korea)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Adders; Compressors; Forestry; MOS Devices; Numbering Systems; Compressor Designs; Gate Models; Hardware Architecture; Hardware Implementations; Low-Power Operation; Modular Arithmetic; Modulo 2; Residue Number System (RNS); Hardware; Compressors; Models; Trees; Modulo 2n+1 Squarer; Sparse Tree Adder; Unit Gate Model

International Standard Book Number (ISBN)

9781479951277

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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