Title

Asynchronous Circuit Design using New High Speed NCL Gates

Abstract

The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level topologies of conventional NCL gates have weakness of logic speed, area overhead or wire complexity. Therefore, this paper proposes a new NCL gates designed at transistor level for high-speed, low area overhead. A 4 x 4 multiplier using the proposed NCL gates has been compared to the multiplier using conventional NCL gates in terms of delay, area and energy consumption.

Meeting Name

International SoC Design Conference: ISOCC (2014: Nov. 3-6, Jeju, South Korea)

Department(s)

Electrical and Computer Engineering

Sponsor(s)

IC Design Education Center (IDEC)

Comments

This work was supported by IC Design Education Center (IDEC).

Keywords and Phrases

Asynchronous Sequential Logic; Design; Differentiating Circuits; Energy Utilization; Formal Logic; Integrated Circuit Manufacture; Multiplying Circuits; Area Overhead; Asynchronous Circuit Design; Asynchronous Circuit; Asynchronous Logic Design; Multiplier; NCL; Null Convention Logic; Transistor Level; Logic Circuits; Delay Insensitive Model

International Standard Book Number (ISBN)

9781479951260; 9781479951277

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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