Adaptive Multi-Path BCH Decoder to Alleviate Hotspot-Induced DRAM Bit Error Variation in 3D Heterogeneous Processor

Abstract

A 3D heterogeneous processor (commonly termed as 3DHP) integrates multiple processor (such as CPU/GPU) and DRAM dies, interconnected vertically by a massive number of Through-Silicon Vias (TSVs). The 3DHP is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error variation in DRAM dies. This work proposes a novel adaptive multi-path BCH decoder to efficiently address this issue. Instead of having a static BCH decoder designed from the worst-case bit error probability analysis, the proposed adaptive multi-path BCH decoder offers multiple decoding paths with varying target number of error bits to correct, which is estimated from the thermal gradient data generated by on-chip temperature sensors. Thus, it minimizes the overall decoding latency adaptively. The proposed approach has been verified by implementing an adaptive 4-path BCH decoder in FPGA hardware. A series of decoding performance evaluation data has been generated to demonstrate the efficiency of the proposed design.

Department(s)

Electrical and Computer Engineering

Sponsor(s)

National Science Foundation (U.S.)

Comments

This research work has been supported in part by NSF grants: CCF-1337167 and CCF-1539840.

Keywords and Phrases

Decoding; Electronics Packaging; Energy Utilization; Errors; Thermal Gradients; Three Dimensional Integrated Circuits; BCH Decoder; Bit Error Probability Analysis; Decoding Performance; Heterogeneous Processors; Multiple Decoding Paths; Spatial and Temporal Variability; Thermal Integrity; Through Silicon Vias; Bit Error Rate; 3D Heterogeneous Processor; Bit Error Rate Variability

International Standard Serial Number (ISSN)

1598-1657; 2233-4866

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2017 Institute of Electronics Engineers of Korea, All rights reserved.

Publication Date

01 Oct 2017

Share

 
COinS