A Fast Low-Power Modulo 2n + 1 Multiplier Design
Modulo 2n + 1 multipliers are the primitive computational logic components widely used in residue arithmetic, digital signal processing and cryptography. In this work, a fast low-power hardware implementation of modulo 2n + 1 multiplier is proposed and validated. The proposed hardware architecture is based on the efficient compressors and modulo carry lookahead adders as the basic building blocks. The modulo carry lookahead adder uses the sparse-tree adder technique to achieve better speed. The resulting implementations are compared both qualitatively and quantitatively, in standard CMOS cell technology, with the existing implementations. The results show that the proposed implementation is considerably faster and consume significantly less power than similar hardware implementations making them a viable option for efficient designs.
R. R. Modugu et al., "A Fast Low-Power Modulo 2n + 1 Multiplier Design," Proceedings of the IEEE International Instrumentation and Measurement Technology Conference (2009, Singapore), pp. 957-961, Institute of Electrical and Electronics Engineers (IEEE), May 2009.
The definitive version is available at https://doi.org/10.1109/IMTC.2009.5168589
IEEE International Instrumentation and Measurement Technology Conference: I2MTC (2009: May 5-7, Singapore)
Electrical and Computer Engineering
Keywords and Phrases
Basic Building Block; Carry Look-Ahead Adder; Cell Technology; Computational Logic; Efficient Designs; Hardware Architecture; Hardware Implementations; International Data Encryption Algorithm (IDEA); Low Power; Lowpower Hardware; Modulo 2; Modulo Multiplier; Multiplier Design; Residue Arithmetic; Standard CMOS; Compressors; Computational Efficiency; Cryptography; Frequency Multiplying Circuits; Hardware; Measurement Theory; Signal Processing; Adders; Sparse-Tree Adder
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