A Fast Low-Power Modulo 2ⁿ + 1 Multiplier Design

Abstract

Modulo 2n + 1 multipliers are the primitive computational logic components widely used in residue arithmetic, digital signal processing and cryptography. In this work, a fast low-power hardware implementation of modulo 2n + 1 multiplier is proposed and validated. The proposed hardware architecture is based on the efficient compressors and modulo carry lookahead adders as the basic building blocks. The modulo carry lookahead adder uses the sparse-tree adder technique to achieve better speed. The resulting implementations are compared both qualitatively and quantitatively, in standard CMOS cell technology, with the existing implementations. The results show that the proposed implementation is considerably faster and consume significantly less power than similar hardware implementations making them a viable option for efficient designs.

Meeting Name

IEEE International Instrumentation and Measurement Technology Conference: I2MTC (2009: May 5-7, Singapore)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Basic Building Block; Carry Look-Ahead Adder; Cell Technology; Computational Logic; Efficient Designs; Hardware Architecture; Hardware Implementations; International Data Encryption Algorithm (IDEA); Low Power; Lowpower Hardware; Modulo 2; Modulo Multiplier; Multiplier Design; Residue Arithmetic; Standard CMOS; Compressors; Computational Efficiency; Cryptography; Frequency Multiplying Circuits; Hardware; Measurement Theory; Signal Processing; Adders; Sparse-Tree Adder

International Standard Book Number (ISBN)

978-1424433520

International Standard Serial Number (ISSN)

1091-5281

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2009 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2009

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