Time Domain PDN Noise Modeling for High Performance System
In this paper, we investigate the impact of the PDN inductance/impedance as well as the decoupling capacitors location on the initial IC noise voltage drop for a high performance system. To consider a worst case situation for the noise voltage at the integrated circuit (IC) we set the on-chip capacitance to zero. The impact of the delay due to remote location of the decoupling capacitors for fast rise-time current waveforms is also studied.
H. Jin et al., "Time Domain PDN Noise Modeling for High Performance System," Proceedings of the 25th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (2016, San Diego, CA), pp. 61-63, Institute of Electrical and Electronics Engineers (IEEE), Oct 2016.
The definitive version is available at http://dx.doi.org/10.1109/EPEPS.2016.7835418
25th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (2016: Oct. 23-26, San Diego, CA)
Electrical and Computer Engineering
Keywords and Phrases
Capacitance; Electronics Packaging; Decoupling Capacitor; Fast Rise Time; High Performance Systems; On-Chip Capacitance; Power Distribution Modeling; Power Integrity; PPP Solver; Remote Location; Integrated Circuits; Power Integrity Analysis; Capacitors; Inductance; Time-Domain Analysis; Delays; Impedance; Pins; Waveform Analysis; Electric Impedance; Inductance; Integrated Circuit Interconnections; Integrated Circuit Noise; Power Integrated Circuits; Rise-Time Current Waveforms; Time Domain PDN Noise Modeling; High Performance System; PDN Inductance Impact; PDN Impedance Impact; Decoupling Capacitor Location; IC Noise Voltage Drop; Noise Voltage; Delay Impact
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Article - Conference proceedings
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