Power/Ground Pin-Map Design for Power Integrity
In this paper, a simple circuit model for IC multiple power and ground via arrays in a multilayer PCB is built based on the resonant cavity model. Using the circuit model, the parasitic inductance for the IC power and ground connection is quantitatively investigated according to via number and via patterns. The stack-up configuration of the power/ground plane pair is not critical for PDN performance in multilayer PCBs, as long as there are sufficient IC power/ground vias in an alternating pattern. The outcome of this work can be used to guide the pin-map design for high-speed packages.
J. Kim et al., "Power/Ground Pin-Map Design for Power Integrity," Proceedings of the ASME Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems (2011, Portland, OR), vol. 1, pp. 675-679, American Society of Mechanical Engineers (ASME), Jul 2011.
The definitive version is available at http://dx.doi.org/10.1115/IPACK2011-52287
ASME Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems (2011: Jul. 6-8, Portland, OR)
Electrical and Computer Engineering
Keywords and Phrases
Circuit Models; Ground Connections; High-Speed; Parasitic Inductances; Power Integrity; Power/Ground Plane Pair; Simple Circuits; Circuit Theory; Exhibitions; Multilayers; Organic Pollutants; Polychlorinated Biphenyls; Maps
International Standard Book Number (ISBN)
Article - Conference proceedings
© 2011 American Society of Mechanical Engineers (ASME), All rights reserved.