Title

Inductance Extraction for PCB Prelayout Power Integrity using PMSR Method

Abstract

Proper power integrity (PI) analysis is required for printed circuit board (PCB) power distribution network (PDN) design. Top-layer interconnect inductance for PI has always been a vital concern for high-speed industry. Developing a simple physics-based equivalent circuit model for critical structures is essential for understanding the physics of the system and for intelligent designs. In this paper, a physics-based model size reduction (PMSR) method is applied to get the equivalent circuit model for the above-ground geometries. The extracted physics-based models are also based on the partial element equivalent circuit (PEEC) method, and can be used in analyzing the structure in its parts. By applying PMSR method, a physics-based equivalent circuit model can be proposed and this circuit model is related to the geometric features of the design. In this way, PMSR method can provide an intuitive guideline in designing PCB and reducing above inductances, therefore, a low-ripple dc voltage can be delivered through PDN. Taking advantage of PEEC and PMSR methods, the top-layer inductances of three different geometries are calculated and the physics-based circuit models are obtained, respectively.

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Sponsor(s)

National Science Foundation (U.S.)
Research Grants Council (Hong Kong, China)
National Natural Science Foundation (China)
University Grants Committee (Hong Kong, China)

Comments

This work was supported in part by the National Science Foundation under Grant IIP-1440110, in part by the Research Grants Council of Hong Kong under Grant GRF 716713, Grant GRF 17207114, and Grant GRF 17210815, in part by the Natural Science Foundation of China under Grant 61271158, and in part by the Hong Kong University Grant Council under Grant AoE/P-04/08.

Keywords and Phrases

Circuit Simulation; Circuit Theory; Equivalent Circuits; Geometry; Inductance; Printed Circuit Boards; Printed Circuit Design; Equivalent Circuit Model; Inductance Extraction; Interconnect Inductance; Partial-Element Equivalent-Circuit Methods; Physics-Based Circuit Models; Physics-Based Modeling; Power Distribution Network; Printed Circuit Boards (PCB); Electric Network Analysis; Partial Element Equivalent Circuit (PEEC); Physics-Based Model Size Reduction (PMSR); Power Distribution Network (PDN); Top-Layer Inductance

International Standard Serial Number (ISSN)

0018-9375;1558-187X

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2017 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Share

 
COinS