Determination of Copper Foil Surface Roughness from Micro-Section Photographs
Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important. Currently, there is no method for adequately quantifying roughness of a signal trace or a power/reference plane layer within a finished PCB. The measurement methods currently available can only be applied to the base foil, prior to its incorporation into a finished board, as they require direct access to the surface to be measured. In a PCB, this surface is not directly accessible, as it is encapsulated within the board, and attempting to expose the surface will necessarily damage or destroy both the board and the surface of interest. This paper describes a method by which the surface roughness of a metal foil or conductor layer within a PCB may be determined from a microsectioned sample of the same. A small, non-functional area, e.g. a corner of the PCB, can be removed, and the surface roughness of the circuit layers can be assessed without impairing the function of the PCB. In the proposed method, a conductor (a trace or a plane) in the microsectioned sample is first digitally photographed at high magnification. The digital photo obtained is then used as an input to a signal- and image-processing algorithm within a graphical user interface (GUI). The latter automatically computes and returns the surface roughness values of the layer photographed. The tool enables the user to examine the surface textures of the two sides of the conductor independently. In the case of a trace, the composite value of roughness, based on the entire perimeter of the trace cross-section can be calculated.
S. Hinaga et al., "Determination of Copper Foil Surface Roughness from Micro-Section Photographs," Proceedings of the IPC APEX EXPO (2012, San Diego, CA), vol. 3, pp. 1556-1590, IPC (Organization), Mar 2012.
IPC APEX EXPO (2012: Feb. 28-Mar. 1, San Diego, CA)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
A-Plane; Conductor Layers; Copper Conductors; Copper Foils; Digital Photos; High-Speed; Image-Processing Algorithms; Manufacturing Process; Measurement Methods; Non-Functional; Plane Layers; Signal Integrity; Signal Traces; Surface Textures; Copper; Exhibitions; Graphical User Interfaces; Photography; Printed Circuit Manufacture; Surface Roughness; Printed Circuit Boards
International Standard Book Number (ISBN)
Article - Conference proceedings
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