DC-DC buck converter EMI reduction using PCB layout modification

Abstract

The paper treats the effect of layout on the electromagnetic interference (EMI) of buck converters. An optimized layout design for dc-dc synchronous buck converter is proposed for EMI reduction. Six different layout versions are analyzed with respect to loop area, loop inductance, radiating dipole moments, and far-field radiation. Optimizations are done with respect to field-effect transistor (FET), decoupling capacitor and via placement. Passive full-wave simulations are used to estimate and verify the loop inductance and far-field emissions. Those are compared with measurements. A gigahertz transverse electromagnetic (GTEM) cell is used to quantify the dipole moments in the printed circuit board (PCB) for estimating the far field and comparing to measurement.

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Buck Converters; DC-DC Buck Converter; Decoupling Capacitor; EMI Reductions; EMI/EMC; Far-field; Far-field Radiation; Full-wave Simulations; Gigahertz Transverse Electromagnetic Cells; Layout Designs; Layout Modification; Loop Inductance; Radiating Dipole; Synchronous Buck Converter; Via Placements; Electric Dipole Moments; Electromagnetic Pulse; Electromagnetism; Field Effect Transistors; Inductance; Optimization; Printed Circuit Boards; DC-DC Converters; PCB Layout

International Standard Serial Number (ISSN)

0018-9375; 1558-187X

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2011 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jul 2011

Link to Full Text

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