Title

A Novel Method for ESD Soft Error Analysis on Integrated Circuits using a TEM Cell

Abstract

The ultimate goal of this work is to predict ESD system level behavior. A methodology which can evaluate the IC immunity in terms of ESD-induced soft error is introduced. A modified TEM cell and a simple test board with a memory IC are designed for this purpose. The correlation between product level ESD standard test and the proposed IC immunity test is discussed.

Meeting Name

34th Electrical Overstress/Electrostatic Discharge Symposium (2012: Sep. 9-14, Tucson, AZ)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Immunity Test; Soft Error; Standard Tests; System Levels; TEM Cell; Electrostatic Discharge; Error Analysis; Electrostatic Devices

International Standard Book Number (ISBN)

1585372188; 9781585372188

International Standard Serial Number (ISSN)

0739-5159

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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