Title

Modeling Timing Variations in Digital Logic Circuits Due to Electrical Fast Transients

Abstract

Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, like an electrical fast transient (EFT). Soft failures in these cases are often caused by timing errors in the IC, for example when delays through logic become too large to meet internal timing constraints. Methods are needed to predict when these failures will occur. A closed-form expression is proposed in this paper to predict the change in propagation delay through logic as a result of an EFT on the IC power supply. The expression uses process parameters that can be found from SPICE models of FETs within the IC or through external measurements of the IC when SPICE models are unavailable. The model is used to predict the frequency of a CMOS ring oscillator manufactured in 0.5 um technology. Predicted results closely match those found through measurements with a maximum relative error of approximately 1%.

Meeting Name

2013 IEEE International Symposium on Electromagnetic Compatibility (2013: Aug. 5-9, Denver, CO)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Integrated Circuit Modeling; Power Supplies; Propagation Delay; Predictive Models; Ring Oscillators; Frequency Measurement

International Standard Book Number (ISBN)

978-1-4799-0408-2

International Standard Serial Number (ISSN)

2158-110X

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2013 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Share

 
COinS