Modeling of On-Chip Power Distribution Network

Author

Chulsoon Hwang, Missouri University of Science and TechnologyFollow
Jingook Kim
Jun Fan, Missouri University of Science and TechnologyFollow
Joungho Kim
James L. Drewniak, Missouri University of Science and TechnologyFollow

Abstract

Because of its nature, the approach to an on-chip power distribution network (PDN) is quite different from that of an off-chip PDN. In this chapter, on-chip PDN modeling is discussed. We begin Section 5.2 by modeling on-chip capacitors. Section 5.3 extracts the electrical characteristics of the on-chip wires forming the PDN. Section 5.4 is devoted to an off-chip PDN incorporating PCB and vias. Section 5.5 investigates the power supply induced jitter. The signal output is contaminated by the supply voltage fluctuation; the trends are analyzed at the transistor level and physically understood.

Recommended Citation

C. Hwang et al., "Modeling of On-Chip Power Distribution Network," Noise Coupling in System-on-Chip, pp. 93 - 138, CRC Press, Dec 2017.

Department(s)

Electrical and Computer Engineering

Comments

Chapter 5 in Noise Coupling in System-on-Chip, editor Thomas Noulis

International Standard Book Number (ISBN)

978-149879677-4

Document Type

Book - Chapter

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2017 CRC Press, All rights reserved.

Publication Date

01 Dec 2017