Title

A 6.4Gbps On-Chip Eye Opening Monitor Circuit for Signal Integrity Analysis of High Speed Channel

Abstract

In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm.

Meeting Name

IEEE International Symposium on Electromagnetic Compatibility, EMC 2008 (2008: Aug. 18-22, Detroit, MI)

Department(s)

Electrical and Computer Engineering

International Standard Book Number (ISBN)

978-1-4244-1699-8

International Standard Serial Number (ISSN)

2158-110X

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 20018 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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