Title

Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects

Abstract

In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN.

Department(s)

Electrical and Computer Engineering

Comments

This work was supported by the MKE/KEIT through the IT R&D Program "Wafer Level 3-D IC Design and Integration" under Grant KI001472, the MKE/KEIT through the IT R&D program "Core Process Development of the 3-D Integration for System IC" under Grant 10039232, and the Smart IT Convergence System Research Center funded by the Ministry of Education, Science and Technology through the Global Frontier Project STRC-2011-0031863.

Keywords and Phrases

3-D Stacked On-Chip Power Distribution Network (PDN); On-Chip Decoupling Capacitor (Decap); On-Chip PDN; PDN Impedance; Power/ground (P/G) TSV; Silicon Substrate; Through Silicon Via (TSV)-Based 3-D ICs

International Standard Serial Number (ISSN)

2156-3950

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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