On-Chip Linear Voltage Regulator Module (VRM) Effect on Power Distribution Network (PDN) Noise and Jitter at High-Speed Output Buffer

Abstract

In this paper, the reduction of power distribution network noise and jitter at high-speed output buffer by using on-chip linear voltage regulator module circuit is introduced and analyzed. The transient response of typical on-chip linear VRM circuit is analyzed in power gating condition. When the on-chip linear VRM circuit is inserted between on-chip PDN and operating high-speed output buffers, the on-chip PDN noise and jitter at output buffer are significantly reduced. The larger on-chip decoupling capacitor leads to the lower PDN noise generated by on-chip linear VRM circuit. The on-chip linear VRM also reduces the impact of the aggressor buffer to the victim buffer in different PDN, resulting in the improved performance of the victim buffer. Reduction of PDN noise and jitter at output buffer using on-chip linear VRM are validated based on SPICE simulation with 110 nm CMOS technology library.

Meeting Name

2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity (2015: Mar. 15-20, Santa Clara, CA)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Second Research Center/Lab

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Jitter; On-Chip Linear Voltage Regulator Module (VRM); Power Distribution Network (PDN); PDN Noise; System-On-Chip; Noise; Jitter; Capacitors; Integrated Circuit Modeling; Transistors; Switches

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2015 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Mar 2015

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