On-Chip Linear Voltage Regulator Module (VRM) Effect on Power Distribution Network (PDN) Noise and Jitter at High-Speed Output Buffer
In this paper, the reduction of power distribution network noise and jitter at high-speed output buffer by using on-chip linear voltage regulator module circuit is introduced and analyzed. The transient response of typical on-chip linear VRM circuit is analyzed in power gating condition. When the on-chip linear VRM circuit is inserted between on-chip PDN and operating high-speed output buffers, the on-chip PDN noise and jitter at output buffer are significantly reduced. The larger on-chip decoupling capacitor leads to the lower PDN noise generated by on-chip linear VRM circuit. The on-chip linear VRM also reduces the impact of the aggressor buffer to the victim buffer in different PDN, resulting in the improved performance of the victim buffer. Reduction of PDN noise and jitter at output buffer using on-chip linear VRM are validated based on SPICE simulation with 110 nm CMOS technology library.
H. Kim et al., "On-Chip Linear Voltage Regulator Module (VRM) Effect on Power Distribution Network (PDN) Noise and Jitter at High-Speed Output Buffer," Proceedings of the 2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity (2015, Santa Clara, CA), Institute of Electrical and Electronics Engineers (IEEE), Mar 2015.
The definitive version is available at http://dx.doi.org/10.1109/EMCSI.2015.7107653
2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity (2015: Mar. 15-20, Santa Clara, CA)
Electrical and Computer Engineering
Center for High Performance Computing Research
Second Research Center/Lab
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Jitter; On-Chip Linear Voltage Regulator Module (VRM); Power Distribution Network (PDN); PDN Noise; System-On-Chip; Noise; Jitter; Capacitors; Integrated Circuit Modeling; Transistors; Switches
Article - Conference proceedings
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